The present invention generally relates to a flip chip assembly apparatus employing induction coils, and more particularly to selective area heating during flip chip assembly.
New integrated circuit technologies include three-dimensional integrated circuits. One type of 3D integrated circuit may include two or more layers of active electronic components stacked vertically and electrically joined with through-substrate vias and solder bumps. The 3D integrated circuit may provide numerous benefits such as increased package density yielding a smaller footprint, and improved bandwidth due to the short connection lengths made possible by the use of through-silicon-vias. The 3D integrated circuit described above may be fabricated in any number of known methods. Some 3D integrated circuits may include a silicon interposer which may be used to re-direct circuitry between a ship carrier and one or more top chips.
Warping or uneven heating of the components of the 3D integrated circuit during typical assembly may result in failed solder bump connections and short circuits. For example, non-wetting and bridging may be a result of warping or uneven heating. The influence warping and uneven heating has on 3D chip packaging may become more significant as the chip size increases and the component thickness decreases.
There are two primary methods for wetting solder bump connections: belt reflow furnaces and flip-chip bonders. A belt reflow furnace works by conveying one or more chips through one or more constant temperature ovens, in order to gradually increase the temperature to the point where the solder material can form a connection. Flip-chip bonders bond only a single chip at a time by quickly ramping up the temperature of the solder material to form connections.